NAND flash memories are used widely as mass storage. In recent years, memory devices have been miniaturized for reducing cost-per-bit and increasing volume-per-bit, and further miniaturization is greatly demanded in this technical field. However, before promoting miniaturization of flash memories, there are many issues to be solved such as the development of lithography techniques and inhibition of the short channel effect, interdevice interference, and interdevice variations. Thus, a miniaturization technique simply directed to improvement of a planar structure will not be enough to sustainably increase storage density of memory devices in future.
Considering the above, techniques to shift such a conventional two-dimensional (planar) structure to a three-dimensional (solid) structure have been developed in recent years for higher memory cell integration, and various kinds of three-dimensional nonvolatile semiconductor storage devices have been proposed. One of them is a vertical gate (VG) semiconductor memory structure which has a layout substantially similar to a two-dimensional NAND layout including peripheral devices and the like, and contacts corresponding to the semiconductor layers and gate contacts can be formed therein at the same time.
The VG semiconductor memory structure can be classified broadly into two types by its memory cell structure. One is a vertical gate-floating gate (VG-FG) type in which charge storage layers are electrically floating, and the other is a vertical gate-metal/oxide/nitride/oxide/silicon (VG-MONOS) type in which charge storage layers trap the charge.
Both types feature a gate stacked layer structure (memory cell) in which a tunnel insulating layer, a charge storage layer, a block insulating layer (IPD layer), and a control gate electrode are stacked in this order on a side surface of a semiconductor layer (channel) on a semiconductor substrate.
In such a VG semiconductor memory structure, writing and erasing of data are performed by a charge transfer between the semiconductor layer as a channel and the floating gate electrode. However, when write/erase operations are repeated, the tunnel insulating layer is damaged (defective), and charge is trapped in the damaged part. The charge trapped inside the tunnel insulating layer varies threshold voltage in the memory cell in a read process. Furthermore, when the charge is detrapped, channel current is varied thereby. These phenomena cause a read error.